Biography
I am a PhD student in Computer Architecture in the area of Cognitive Computing on GPU Architectures. I am carrying out my doctorate, under the supervision of Prof. Antonio Gonzalez and Dr. Jose-Maria Arnau, at the Universitat Politècnica de Catalunya – BarcelonaTech (UPC), working in the Computer Architecture Department enclosed in the ARCO (Architectures and Compilers) research group.
Curriculum Vitae
You might be interested in my curriculum vitae or my LinkedIn page.
You can also find some of my projects at github.
Studies
I received a BSc in Informatics Engineering with specialization in Computer Engineering, and a MSc in Innovation and Research in Informatics with specialization in High Performance Computing, from the UPC – BarcelonaTech.
My master thesis “Characterization of Speech Recognition Systems on GPU Architectures”, was done under the supervision of Prof. Antonio Gonzalez and Dr. Jose-Maria Arnau.
Research
The research for my doctorate focuses on the area of Cognitive Computing, in particular Speech Recognition, as well as Graph Processing on GPU Architectures. My objective is to propose and evaluate architectural extensions to GPU Architectures with the goal to improve energy-efficiency and performance which will enable and empower more precise and capable Automatic Speech Recognition systems (ASR) and improved performance of graph processing algorithms. My current focus is on the improvement of the memory system utilization under graph exploration on GPU architectures.
Topics: Computer Architecture, Graph Algorithms, Stream Compaction, Speech Recognition, ASR, Viterbi, GPU Architectures, Energy-Efficency.
Publications
- “SCU: A GPU Stream Compaction Unit for Graph Processing”. Albert Segura, Jose-Maria Arnau, Antonio Gonzalez. In Proceedings of the 46th International Symposium on Computer Architecture (ISCA), June 2019. ACM
- “Low-Power Automatic Speech Recognition Through a Mobile GPU and a Viterbi Accelerator”. Reza Yazdani, Albert Segura, Jose-Maria Arnau, Antonio Gonzalez. IEEE Micro, vol. 37, no. 1, pp. 22-29, 2017. IEEE Xplore
- “An Ultra Low-Power Hardware Accelerator for Automatic Speech Recognition”. Reza Yazdani, Albert Segura, Jose-Maria Arnau, Antonio Gonzalez. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO-49), October 2016. IEEE Xplore
- “A Linux Kernel Scheduler Extension for Multi-Core Systems”.Aleix Roca, Samuel Rodriguez, Albert Segura, Vicenç Beltran and Kevin Marquet. 26th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC), December 2019.
Honors and Awards
- HiPEAC Paper Award for “SCU: A GPU Stream Compaction Unit for Graph Processing” (ISCA), HiPEAC Network of Excellence. 2019
- HiPEAC Paper Award for “An Ultra Low-Power Hardware Accelerator for Automatic Speech Recognition” (MICRO-49), HiPEAC Network of Excellence. 2016
- Collaboration grant with the Computer Architecture department of UPC BarcelonaTech, Spanish government MECD AGAUR grant. 2014
- Winner of the Fourth “Concurso de Programación Paralela” organized by the University of Murcia, 2014 edition. Albert Segura, Pedro Benedicte. 2014